您的位置：
快3网下载安装到手机 >>
全部标准分类 >>
国外标准 >>
IEEE >>
IEEE 1149.10-2017 IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture

【国外标准】 IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture

本网站发布时间： 2025-04-28

IEEE 1149.10-2017
定价： 104元 / 折扣价： 89 元
在线阅读

开通会员免费在线看70000余条国内标准，赠送文本下载次数，单本最低仅合13.3元！还可享标准出版进度查询、定制跟踪推送、标准查新等超多特权！查看详情>>

标准简介

适用范围：

This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from on-chip test structures. The standard re-uses existing high speed I/O (HSIO) known in the industry for the high speed test access port (HSTAP). The HSIO connects to an on-chip distribution architecture through a common interface. The scope includes the distribution architecture test logic and packet decoder logic. The objective of the distribution architecture and packet decoder is that it can be readily re-used with different integrated circuits (ICs) that host different HSIO technology, such that the standard addresses as large a part of the industry as possible. The scope includes IEEE 1149.1 Boundary-Scan Description Language (BSDL) and Procedural Description Language (PDL) documentation, which can be used for configuring a mission mode HSIO to a test mode compatible with the HSTAP. The same BSDL and PDL can then be used to deliver high-speed data to the on-chip test structures.

基本信息

标准号：
IEEE 1149.10-2017
标准名称：
IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture
英文名称：
标准状态：
发布日期：
实施日期：
出版语种：

标准分类号

标准ICS号：
中标分类号：

关联标准

替代以下标准：
被以下标准替代：
引用标准：
采用标准：

出版信息

页数：
字数：
开本：

其他信息

起草人：
起草单位：
归口单位：
提出部门：
发布部门：

其它标准

推荐标准